1. Technical Field
The present invention relates generally to semiconductor fabrication, and more particularly, to a silicon dioxide removing method useful for fabricating a hetero-junction bipolar transistor (HBT).
2. Related Art
Removal of silicon dioxide (i.e., oxide) is problematic relative to a variety of semiconductor fabrication processes such as fabrication of a raised source/drain complementary metal-oxide semiconductor (CMOS), silicon-on-insulator (SOI) devices, field-effect transistor (FET) gate oxide generation, etc. One illustrative process in which oxide residuals cause significant problems is the fabrication of silicon (Si) NPN and silicon-germanium (SiGe) HBTs. In this application, a thin oxide emitter-base interface traditionally separates the arsenic doped emitter polysilicon from the boron doped single crystal SiGe base. Referring to FIG. 1, a HBT 2 having a thin oxide emitter-base interface 4 is shown. Oxide interface 4 is known to control the holes re-injected back into emitter 6 as base 8 current, and the out-diffusion of arsenic from emitter 6 polysilicon into single crystal base 8. The arsenic out-diffusion forms the actual emitter-base junction in the single crystal silicon base 8. This oxide interface 4 is currently grown using a low temperature rapid thermal oxidation (RTO) process.
Problems related to oxide interface 4 arise relative to reducing emitter resistance (Re) of NPN transistors in conventional silicon-germanium (SiGe) technology. Reducing Re is advantageous because high Re causes collector current to roll off quickly. A thin oxide interface 4 (FIG. 1), described above, and the non-self aligned polysilicon emitter, are known to contribute significantly to Re. One approach to address this problem is to provide deposition of in-situ doped (ISD) arsenic amorphous silicon to form the emitter without an oxide interface. In this case, the amorphous region re-crystalizes off seed silicon of the base because there is no interfacial oxide. This approach reduces Re by as much as five times, and improves high performance HBT device cutoff frequency by approximately 6 GHz. Unfortunately, this approach is unreliable. First, some wafers within a lot exhibit high Re compared to the specified amount using this approach. Second, certain wafers exhibit high trans-wafer variation of Re using this approach. Some of the high Re wafers are also accompanied by lower NPN yield due to interference of oxide residuals at the interface, which causes local strain field distortion and misaligned dislocations. Accordingly, the ISD approach's unreliability makes it difficult for process control during manufacturing.
In view of the foregoing, there is a need in the art for an improved semiconductor cleaning method for removing oxide residuals.